Anyway I need to do some more testing before I can say anything for sure. So it might be possible to use something else that is be better. The openhantek dds-120 port is using bulk transfers.
#SAINSMART DDS140 FIRMWARE DRIVER#
Right now the vendor software is using usb interrupt transfers (my driver also). So if you didn't manage to get the first buffer in time there will be a time discontinuity.
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#SAINSMART DDS140 FIRMWARE FULL#
During that time you need to get the first buffer over to the host because when the second buffer is full the FX2 will start over with the first one. When the buffer is filled it will start filling another buffer. The adc data lines are read by the fx2 and placed in a buffer somewhere on the FX2 chip (lets say 1024 bytes). As far as I understood there is a clock that clocks the adc. And there is a post in this thread where someone says he just started streaming without any start command. One of the lower time resolutions only send one 0x33 packet per 16 data packets. They might always get zeros at the start and then a signal to do the analysis on. The vendor software might do it this way to be able to get a clean part of a continuous stream to analyse. No need to issue a 0x33 command per packet. I can at any time just request more packets without any problem. I think the 0x33 command is a FIFO clear command. I think you are wrong about it using polling. I just sorted out the details which bit to set and found out it was fairly useless. On your blog you list 5 used modes but in your posts you listed 6. Thus I reason that they omitted it in the software. These modes are very close in gain to another gain step. But channel 0 has 0x0A as valid config and Channel 1 has 0x22. Even the software is lying to us when showing "50MHz" (should be "48MHz" -> 24MHz x 2 Channels) Conclusion: 50Mhz -> 48MHz = 24MHz x 2 Channels = 24Msps per Channel 2.4Mhz = 2.4MHz x 2 Channels = 2.4Msps per Channel 240kHz = 240kHz x 2 Channels = 240ksps per Channel The lower samplerates just skip sampling by 1/10, 1/100.
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This can't be true with a 24Mhz clock-source in no way, so we'll end up at 24/48Msps like Hantek. From the specs, this scope should do 50Msps, but only when using both channels - single channel is 25Msps. (I must review the trace at IFCLK and CLKOUT.) Maybe its like: 24Mhz crystal -> PLL (48Mhz) -> /2 divider -> 8051 Core + CLKOUT (24Mhz) -> IFCLK + ADC_CLK (24Mhz) Then the 8051-Core, FIFO, and ADC are running at 24Mhz at all time. Quote from: doctormord on October 23, 2014, 04:26:38 pm Regarding the EZ-USB Technical Reference Manual: page 125, the IFCLK can only output 30/48MHz from its internal source.